EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 541
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
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534
- Current page: 541 of 864
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Altera Corporation
July 2005
Figure 5–43. Page 4 of the Transmitter altlvds MegaWizard Plug-In Manager
Registered Inputs
Check the Register inputs box if the input data to the transmitter is not
registered just before it feeds the transmitter module. You can choose
either tx_clkin or tx_coreclk to clock the transmitter data
(tx_in[]) signal. This serves as the register boundary. The number of
registers used is proportional to the deserialization factor (J). The
Quartus II software places the synchronization registers with the LEs in
the same row and closest to the SERDES circuitry.
Use Common PLL for Transmitter & Receiver
Check the Use Common PLLs for Rx and Tx box to place both the LVDS
transmitter and receiver in the same I/O bank in Stratix devices. The
Quartus II software also allows the transmitter and receiver to share the
PLL when the same input clock is used for both. Although you must
High-Speed Differential I/O Interfaces in Stratix Devices
Stratix Device Handbook, Volume 2
5–69
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