EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 435
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
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534
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Altera Corporation
June 2006
3.3-V PCI-X 1.0 Local Bus - PCI-SIG PCI-X Local Bus
Specification Revision 1.0a
The PCI-X 1.0 standard is used for applications that interface to the PCI
local bus. The standard enables the design of systems and devices that
operate at clock speeds up to 133 MHz, or 1 gigabit per second (Gbps) for
a 64-bit bus. The PCI-X 1.0 protocol enhancements enable devices to
operate much more efficiently, providing more usable bandwidth at any
clock frequency. By using the PCI-X 1.0 standard, devices can be designed
to meet PCI-X 1.0 requirements and operate as conventional 33- and
66-MHz PCI devices when installed in those systems. This standard
requires 3.3-V V
with the 3.3-V PCI-X Specification Revision 1.0a and meet the 133-MHz
operating frequency and timing requirements. The 3.3-V PCI standard
does not require input reference voltages or board terminations. Stratix
and Stratix GX devices support both input and output levels.
3.3-V Compact PCI Bus - PCI SIG PCI Local Bus Specification
Revision 2.3
The Compact PCI local bus specification is used for applications that
interface to the PCI local bus. It follows the PCI Local Bus Specification
Revision 2.3 plus additional requirements in PCI Industrial Computers
Manufacturing Group (PICMG) specifications PICMG 2.0 R3.0,
CompactPCI specification, and the hot swap requirements in PICMG 2.1
R2.0, CompactPCI Hot Swap Specification. This standard has similar
electrical requirements as LVTTL and requires 3.3-V V
Stratix GX devices are compliant with the Compact PCI electrical
requirements. The 3.3-V PCI standard does not require input reference
voltages or board terminations. Stratix and Stratix GX devices support
both input and output levels.
3.3-V 1× AGP - Intel Corporation Accelerated Graphics Port
Interface Specification 2.0
The AGP interface is a platform bus specification that enables high-
performance graphics by providing a dedicated high-speed port for the
movement of large blocks of 3-dimensional texture data between a PC's
graphics controller and system memory. The 1 AGP I/O standard is a
single-ended standard used for 3.3-V graphics applications. The 1 AGP
input standard specifies an input voltage range of
– 0.5 V V
reference voltages or board terminations. Stratix and Stratix GX devices
support both input and output levels.
I
V
CCIO
CCIO.
+ 0.5 V. The 1 AGP standard does not require input
Selectable I/O Standards in Stratix & Stratix GX Devices
Stratix and Stratix GX devices are fully compliant
Stratix Device Handbook, Volume 2
CCIO.
Stratix and
4–7
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