EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 691
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Figure 10–2. Stratix & Stratix GX Architectural Elements
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
Pins
Mega RAM Block is
13 Units Wide and
13 Units High
Figure 10–2
Large block elements use their lower-left corner for the coordinate location.
The Stratix GX architectural elements include transceiver blocks on the right side of the device.
Origin (0, 0)
(0,1,0)
PLL
Figure
(2)
10–2:
shows part of a Stratix and Stratix GX device.
(1,18)
(1,17)
(1,16)
(1,15)
(1,1)
LAB
LAB
LAB
LAB
LAB
(11,18)
(11,17)
(11,16)
(11,15)
Mega RAM (1,2)
(11,1)
LAB
LAB
LAB
LAB
LAB
(12,18)
(12,17)
(12,16)
(12,15)
(12,1)
M512
M512
M512
M512
M512
Transitioning APEX Designs to Stratix & Stratix GX Devices
(13,18)
(13,17)
(13,16)
(13,15)
(13,1)
LAB
LAB
LAB
LAB
LAB
Note (1)
(2)
M4K RAM Blocks are
(14,18)
(14,17)
(14,16)
(14,15)
(14,14)
(14,13)
Two Units Wide and
(14,2)
(14,1)
M4K
M4K
M4K
M4K
M4K
M4K
M4K
M4K
One Unit High
Stratix Device Handbook, Volume 2
(16,18)
(16,17)
(16,16)
(16,15)
(16,14)
(16,13)
(16,2)
(16,1)
LAB
LAB
LAB
LAB
LAB
LAB
LAB
LAB
(2)
and Eight Units High
DSPMULT
DSPMULT
DSPMULT
DSPMULT
is Two Units Wide
DSP Block (17,1)
(17,7,0)
(17,7,1)
(17,5,0)
(17,5,1)
(17,3,0)
(17,3,1)
(17,1,0)
(17,1,1)
and
and
and
and
DSPOUT
(18,1,0)
(18,1,7)
and
10–7
(3)
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