EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 721
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
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534
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Altera Corporation
July 2005
functionality while the system is in operation by reconfiguring the device.
You can also perform in-field upgrades by distributing a new
programming file to system users.
The following sections describe the MSEL[2..0], VCCSEL, PORSEL, and
nIO_PULLUP pins used in Stratix and Stratix GX device configuration.
MSEL[2..0] Pins
You can select a Stratix or Stratix GX device configuration scheme by
driving its MSEL2, MSEL1, and MSEL0 pins either high or low, as shown
in
The MSEL[] pins can be tied to V
ground.
V
You can configure Stratix and Stratix GX devices using the 3.3-, 2.5-, 1.8-,
or 1.5-V LVTTL I/O standard on configuration and JTAG input pins.
VCCSEL is a dedicated input on Stratix and Stratix GX devices that selects
between 3.3-V/2.5-V input buffers and 1.8-V/1.5-V input buffers for
dedicated configuration input pins. A logic low supports 3.3-V/2.5-V
signaling, and a logic high supports 1.8-V/1.5-V signaling. A logic high
can also support 3.3-V/2.5-V signaling. VCCSEL affects the configuration
Notes to
(1)
(2)
(3)
FPP configuration
PPA configuration
PS configuration
Remote/local update FPP
Remote/local update PPA
Remote/local update PS
JTAG-based configuration
Table 11–2. Stratix & Stratix GX Device Configuration Schemes
CCSEL
Table
These schemes require that you drive a secondary pin RUnLU to specify whether
to perform a remote update or local update.
Do not leave MSEL pins floating. Connect them to V
support the non-JTAG configuration scheme used in production. If only JTAG
configuration is used you should connect the MSEL pins to ground.
JTAG-based configuration takes precedence over other configuration schemes,
which means the MSEL pins are ignored.
Pins
11–2.
Table
11–2:
Description
(1)
(1)
(1)
(3)
CCIO
Configuring Stratix & Stratix GX Devices
of the I/O bank they reside in or
Stratix Device Handbook, Volume 2
MSEL2
(2)
0
0
0
1
1
1
C C I O
or GND. These pins
MSEL1
(2)
0
0
1
0
0
1
MSEL0
(2)
0
1
0
0
1
0
11–3
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