EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 441
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
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534
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Altera Corporation
June 2006
f
For more information on the LVDS I/O standard in Stratix devices, see
the High-Speed Differential I/O Interfaces in Stratix Devices chapter.
LVPECL
The LVPECL I/O standard is a differential interface standard requiring a
3.3-V V
graphics, telecommunications, data communications, and clock
distribution. The high-speed, low-voltage swing LVPECL I/O standard
uses a positive power supply and is similar to LVDS, however, LVPECL
has a larger differential output voltage swing than LVDS. The LVPECL
standard does not require an input reference voltage, but it does require
a 100- termination resistor between the two signals at the input buffer.
See
LVPECL. Stratix and Stratix GX devices support both input and output
levels.
Figure 4–14. LVPECL DC Coupled Termination
Figure 4–15. LVPECL AC Coupled Termination
Pseudo Current Mode Logic (PCML)
The PCML I/O standard is a differential high-speed, low-power I/O
interface standard used in applications such as networking and
telecommunications. The standard requires a 3.3-V V
standard consumes less power than the LVPECL I/O standard. The
Figures 4–14
Output Buffer
CCIO.
The standard is used in applications involving video
Output Buffer
10 to 100 nF
10 to 100 nF
and
Selectable I/O Standards in Stratix & Stratix GX Devices
4–15
for two alternate termination schemes for
Z = 50 Ω
Z = 50 Ω
Z = 50 Ω
Z = 50 Ω
100 Ω
100 Ω
Stratix Device Handbook, Volume 2
Input Buffer
R1
R2
V
CCIO
V
CCIO
R1
R2
CCIO
. The PCML I/O
Input Buffer
4–13
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