EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 547
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Figure 5–48. SERDES Bypass LVDS Transmitter with Logic Array as Deserializer
Summary
Altera Corporation
July 2005
Data[7..0]
Clock
PLL
×4 clock
×1 clock
The Stratix device family of flexible, high-performance, high-density
PLDs delivers the performance and bandwidth necessary for complex
system-on-a-programmable-chip (SOPC) solutions. Stratix devices
support multiple I/O protocols to interface with other devices within the
system. Stratix devices can easily implement processing-intensive data-
path functions that are received and transmitted at high speeds. The
Stratix family of devices combines a high-performance enhanced PLD
architecture with dedicated I/O circuitry in order to provide I/O
standard performances of up to 840 Mbps.
Counter
High-Speed Differential I/O Interfaces in Stratix Devices
clock
load
data
data
load
clock
Register
Register
Shift
Shift
data_h
data_l
Stratix Device Handbook, Volume 2
Output
DDR
Serial
data out
tx_clk
5–75
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