EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 594

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Finite Impulse Response (FIR) Filters
Figure 7–9. TDM FIR Filter Implementation
Note to
(1)
7–16
Stratix Device Handbook, Volume 2
Clock input
(1x clock)
x(n)
x x
To increase the DSP block performance, include the pipeline and output registers. See
details.
Figure
Shift register
D
D
D
D
D
D
D
7–9:
PLL
Q
Q
Q
Q
Q
Q
Q
1x clock
2x clock
If the TDM factor is more than 2, then a multiply-accumulator needs to be
implemented. This multiply-accumulator can be implemented using the
soft logic outside the DSP block if all the multipliers of the DSP block are
needed. Alternatively, the multiply-accumulator may be implemented
inside the DSP block if all the multipliers of the DSP block are not needed.
The accumulator needs to be zeroed at the start of each new sample input.
The user also needs a way to store additional sample inputs in memory.
For example, consider a sample rate of r and TDM factor of 4. Then, the
Filter coefficients
RAM / ROM 0
RAM / ROM 2
RAM / ROM 1
Note (1)
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
DSP block
Figure 7–3 on page 7–8
Altera Corporation
D
Accumulator
September 2004
Q
Filter output
y(n)
for