EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 512
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 512 of 864
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Source-Synchronous Timing Budget
Figure 5–26. Output Timing Waveform
Note to
(1)
5–40
Stratix Device Handbook, Volume 2
Output Clock
(Differential
Signal)
Output Data
TPPos0 (max)
TPPos1 (max)
TPPos2 (max)
TPPos3 (max)
TPPos4 (max)
TPPos5 (max)
TPPos6 (max)
TPPos7 (max)
TPPos0 (min)
TPPos1 (min)
TPPos2 (min)
TPPos3 (min)
TPPos4 (min)
TPPos5 (min)
TPPos6 (min)
TPPos7 (min)
The timing specifications are referenced at a 250-mV differential voltage.
Figure
5–26:
Previous Cycle
bit 0
Output Timing
The output timing waveform in
between the output clock and the serial output data stream.
Receiver Skew Margin
Change in system environment, such as temperature, media (cable,
connector, or PCB) loading effect, a receiver's inherent setup and hold,
and internal skew, reduces the sampling window for the receiver. The
timing margin between receiver’s clock input and the data input
sampling window is known as RSKM.
relationship between the parameter and the receiver’s sampling window.
bit 1
MSB
bit 2
Note (1)
bit 3
bit 4
bit 5
Current Cycle
Figure 5–26
bit 6
Figure 5–27
illustrates the relationship
bit 7
illustrates the
Altera Corporation
LSB
July 2005
Cycle
Next
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