EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 758
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
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534
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Configuration Schemes
Figure 11–21. Multi-Device JTAG Configuration
Notes to
(1)
(2)
(3)
(4)
(5)
11–40
Stratix Device Handbook, Volume 2
MasterBlaster or ByteBlasterMV
Stratix, Stratix GX, APEX
same JTAG chain for device programming and configuration.
For more information on all configuration pins connected in this mode, see
Connect the nCONFIG, MSEL0, MSEL1, and MSEL2 pins to support a non-JTAG configuration scheme. If only JTAG
configuration is used, connect nCONFIG to V
to either high or low.
V
MasterBlaster Serial/USB Communications Cable Data Sheet for this value.
nCE must be connected to GND or driven low for successful JTAG configuration.
10-Pin Male Header
Pin 1
IO
is a reference voltage for the MasterBlaster output driver. V
Figure
V CC
11–21:
1 kΩ
(4)
VIO
1 kΩ
1 kΩ
VCC
V CC
(5)
(3)
(3)
(3)
(3)
(3)
(3)
V CC
TM
10 kΩ
JTAG-chain device programming is ideal when the PCB contains multiple
devices, or when testing the PCB using JTAG BST circuitry.
shows multi-device JTAG configuration.
The nCE pin must be connected to GND or driven low during JTAG
configuration. In multi-device PS, FPP and PPA configuration chains, the
first device's nCE pin is connected to GND while its nCEO pin is connected
to nCE of the next device in the chain. The last device's nCE input comes
from the previous device, while its nCEO pin is left floating. After the first
device completes configuration in a multi-device configuration chain, its
nCEO pin drives low to activate the second device's nCE pin, which
prompts the second device to begin configuration. Therefore, if these
devices are also in a JTAG chain, you should make sure the nCE pins are
connected to GND during JTAG configuration or that the devices are JTAG
configured in the same order as the configuration chain. As long as the
devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO of the previous device drives nCE of the
next device low when it has successfully been JTAG configured.
II, APEX 20K, Mercury
nSTATUS
DATA0
DCLK
nCONFIG
MSEL2
MSEL1
MSEL0
nCE
TDI
TMS
Stratix Device
CONF_DONE
TCK
10 kΩ
TDO
CC
V CC
, and MSEL0, MSEL1, and MSEL2 to ground. Pull DATA0 and DCLK
Notes
(5)
TM
(3)
(3)
(3)
(3)
(3)
(3)
, ACEX
V CC
(1),
10 kΩ
TDI
nSTATUS
DATA0
DCLK
nCONFIG
MSEL2
MSEL1
MSEL0
nCE
TMS
(2)
®
Stratix Device
1K, and FLEX
IO
CONF_DONE
TCK
should match the device’s V
10 kΩ
TDO
V CC
®
Table 11–11 on page
10K devices can be placed within the
(5)
(3)
(3)
(3)
(3)
(3)
(3)
V CC
10 kΩ
TDI
nSTATUS
DATA0
DCLK
nCONFIG
MSEL2
MSEL1
MSEL0
nCE
TMS
Stratix Device
CONF_DONE
Altera Corporation
TCK
CCIO
11–37.
. See the
Figure 11–21
TDO
July 2005
V CC
10 kΩ
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