EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 545
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Altera Corporation
July 2005
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M512 Mode
Table 5–18. Address Counters for SERDES Bypass LVDS Receiver
Table 5–19. Address Counters for SERDES Bypass LVDS Transmitter
Table 5–20. Address & Counter Width
M512 Mode
M512 Mode
Write Counter
Width
Deserialization
Deserialization
4
5
6
5
Factor
Factor
16
16
4
8
8
4
8
8
For the transmitter, the read counter is the fast counter and the write
counter is the slow counter. For the receiver, the write counter is the fast
counter and the read counter is the slow counter.
provide the address counter configurations for the transmitter and the
receiver, respectively.
In different M512 memory configurations, the counter width is smaller
than the address width, so you must ground some of the most significant
address bits.
width, and the number of bits to be grounded.
Read Counter
Width
3
3
3
3
Width
Width
Write Up-Counter
Write Up-Counter
(Fast Counter)
(Fast Counter)
4
5
5
6
4
5
5
6
Table 5–20
Write Address
Width
High-Speed Differential I/O Interfaces in Stratix Devices
Starts at
Starts at
8
8
7
8
0
0
0
0
0
0
0
0
summarizes the address width, the counter
Read Address
Width
Width
Read Up-Counter
Read Up-Counter
(Slow Counter)
(Slow Counter)
Width
3
3
3
3
3
3
3
3
7
6
5
5
Stratix Device Handbook, Volume 2
Starts at
Starts at
Write Address Read Address
2
2
2
2
2
2
2
2
Number of Grounded Bits
Tables 5–18
4
3
1
3
Invalid Initial Cycles
Invalid Initial Cycles
Write
Write
12
24
24
48
2
2
2
2
and
Read
Read
4
3
2
2
5–19
16
6
6
6
6
4
8
8
5–73
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