EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 493
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Figure 5–14. Fast PLL Block Diagram
Notes to
(1)
(2)
Altera Corporation
July 2005
Global or
regional clock
In high-speed differential I/O mode, the high-speed PLL clock feeds the SERDES. Stratix devices only support one
rate of data transfer per fast PLL in high-speed differential I/O mode.
Control signal for high-speed differential I/O SERDES.
Clock Input
Figure
5–14:
Frequency
Detector
Phase
You can multiply the input clock by a factor of 1 to 16. The multiplied
clock is used for high-speed serialization or deserialization operations.
Fast PLL specifications are shown in the Stratix Device Family Data Sheet
section of the Stratix Device Handbook, Volume 1. The voltage controlled
oscillators (VCOs) are designed to operate within the frequency range of
300 to 840 MHz, to provide data rates of up to 840 Mbps.
High-Speed Phase Adjust
There are eight phases of the multiplied clock at the PLL output, each
delayed by 45° from the previous clock and synchronized with the
original clock. The three multiplexers (shown in
the delayed, multiplied clocks. The PLL output drives the three counters
k, v, and l. You can program the three individual post scale counters (k, v,
and l) independently for division ratio or phase. The selected PLL output
is used for the serialization or deserialization process in SERDES.
Charge
Pump
Loop
Filter
High-Speed Differential I/O Interfaces in Stratix Devices
VCO Phase Selection
Selectable at each PLL
Output Port
÷ m
VCO
8
Stratix Device Handbook, Volume 2
rxclkin
Post-Scale
Counters
÷ k
÷ v
÷ l
Figure
5–14) select one of
DIFFIOCLK1 (1)
Regional clock
TXLOADEN (2)
RXLOADEN (2)
Regional clock
DIFFIOCLK2 (1)
Global or
regional clock
5–21
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