EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 298
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Contents
Chapter 5. High-Speed Differential I/O Interfaces in Stratix Devices
vi
Drive Strength ...................................................................................................................................... 4–26
Hot Socketing ....................................................................................................................................... 4–27
I/O Termination .................................................................................................................................. 4–28
I/O Pad Placement Guidelines .......................................................................................................... 4–30
Power Source of Various I/O Standards ......................................................................................... 4–38
Quartus II Software Support .............................................................................................................. 4–38
Conclusion ............................................................................................................................................ 4–42
More Information ................................................................................................................................ 4–42
References ............................................................................................................................................. 4–42
Introduction ............................................................................................................................................ 5–1
Stratix I/O Banks ................................................................................................................................... 5–1
Principles of SERDES Operation ......................................................................................................... 5–6
Using SERDES to Implement DDR ................................................................................................... 5–13
Using SERDES to Implement SDR .................................................................................................... 5–14
Differential I/O Interface & Fast PLLs ............................................................................................. 5–16
Mixing Voltage Referenced & Non-Voltage Referenced Standards ....................................... 4–25
Standard Current Drive Strength ................................................................................................. 4–26
Programmable Current Drive Strength ...................................................................................... 4–27
DC Hot Socketing Specification ................................................................................................... 4–28
AC Hot Socketing Specification ................................................................................................... 4–28
Voltage-Referenced I/O Standards ............................................................................................. 4–28
Differential I/O Standards ............................................................................................................ 4–29
Differential Termination (RD) ...................................................................................................... 4–29
Transceiver Termination ............................................................................................................... 4–30
Differential Pad Placement Guidelines ....................................................................................... 4–30
VREF Pad Placement Guidelines ................................................................................................. 4–31
Output Enable Group Logic Option in Quartus II .................................................................... 4–34
Toggle Rate Logic Option in Quartus II ...................................................................................... 4–35
DC Guidelines ................................................................................................................................. 4–35
Compiler Settings ........................................................................................................................... 4–38
Device & Pin Options .................................................................................................................... 4–39
Assign Pins ...................................................................................................................................... 4–39
Programmable Drive Strength Settings ...................................................................................... 4–40
I/O Banks in the Floorplan View ................................................................................................. 4–40
Auto Placement & Verification of Selectable I/O Standards ................................................... 4–41
Stratix Differential I/O Standards ................................................................................................. 5–2
Stratix Differential I/O Pin Location ............................................................................................. 5–5
Stratix Differential I/O Receiver Operation ................................................................................. 5–7
Stratix Differential I/O Transmitter Operation ........................................................................... 5–9
Transmitter Clock Output ............................................................................................................. 5–10
Divided-Down Transmitter Clock Output ................................................................................. 5–10
Center-Aligned Transmitter Clock Output ................................................................................ 5–11
SDR Transmitter Clock Output .................................................................................................... 5–12
Clock Input & Fast PLL Output Relationship ............................................................................ 5–18
Fast PLL Specifications .................................................................................................................. 5–20
Stratix Device Handbook, Volume 2
Altera Corporation
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