EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 651

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 8–5. Stratix & Stratix GX Device XSBI Implementation
Altera Corporation
July 2005
Logic Array
Stratix GX
Stratix &
Data
Data
Stratix & Stratix GX PCS
Transmitter
Receiver
Implementation
The 16-bit full duplex LVDS implementation of XSBI in Stratix devices is
shown in
The source-synchronous I/O implemented in Stratix GX devices
optionally includes dynamic phase alignment (DPA). DPA automatically
and continuously tracks fluctuations caused by system variations and
self-adjusts to eliminate the phase skew between the multiplied clock and
the serial data, allowing for data rates of 1 Gbps. In non DPA mode the
I/O behaves similarly to that of the Stratix I/O. This document assumes
that DPA is disabled. However, it is simple to implement the same system
with DPA enabled to take advantage of its features. For more information
on DPA, see the Stratix GX Transceivers chapter in the Stratix GX Device
Handbook, Volume 1.
PLL2
PLL1
÷8
Transmitter
SERDES
Receiver
SERDES
÷8
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Figure
Phase Shift
180˚
8–5.
×1
PMA_TXCLK_SRC
PMA_RXCLK
PMA_TXCLK
RX_D[15..0]
TX_D[15..0]
Stratix Device Handbook, Volume 2
PMA
Transmitter
Receiver
8–7