EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 189

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Timing Model
Altera Corporation
January 2006
The DirectDrive
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix device densities and speed grades. This section
describes and specifies the performance, internal, external, and PLL
timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary.
Stratix device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under worst-
case voltage and junction temperature conditions.
Table 4–35. Stratix Device Timing Model Status
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Device
technology and MultiTrack
Preliminary
Table 4–35
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
interconnect ensure
shows the status of the
Final
v
v
v
v
v
v
v
4–19