EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 95

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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0
Figure 2–48. EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups
Altera Corporation
July 2005
IO_CLKM[7:0]
IO_CLKO[7:0]
IO_CLKN[7:0]
IO_CLKP[7:0]
8
8
8
8
IO_CLKA[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKL[7:0]
You can use the Quartus II software to control whether a clock input pin
is either global, regional, or fast regional. The Quartus II software
automatically selects the clocking resources if not specified.
Enhanced & Fast PLLs
Stratix devices provide robust clock management and synthesis using up
to four enhanced PLLs and eight fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock-
frequency synthesis. With features such as clock switchover, spread
spectrum clocking, programmable bandwidth, phase and delay control,
and PLL reconfiguration, the Stratix device’s enhanced PLLs provide you
with complete control of your clocks and system timing. The fast PLLs
8
IO_CLKB[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKK[7:0]
8
IO_CLKC[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
8
IO_CLKJ[7:0]
8
IO_CLKD[7:0]
22 Clocks in the
22 Clocks in the
Half-Quadrant
Half-Quadrant
Stratix Device Handbook, Volume 1
8
IO_CLKI[7:0]
8
Stratix Architecture
8
8
8
8
IO_CLKE[7:0]
IO_CLKF[7:0]
IO_CLKG[7:0]
IO_CLKH[7:0]
I/O Clock Regions
2–81