EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 270

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
0
PLL Specifications
4–100
Stratix Device Handbook, Volume 1
f
f
f
f
f
t
t
t
t
t
m
l0, l1, g0
t
f
f
f
f
f
t
t
t
IN
INPFD
OUT
OUT_DIFFIO
VCO
INDUTY
INJITTER
DUTY
JITTER
LOCK
ARESET
IN
INPFD
OUT
OUT_DIFFIO
VCO
INDUTY
INJITTER
DUTY
Table 4–131. Fast PLL Specifications for -5 & -6 Speed Grade Devices
Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 1 of 2)
Symbol
Symbol
CLKIN frequency (1), (2),
Input frequency to PFD
Output frequency for internal global or
regional clock
Output frequency for external clock
driven out on a differential I/O data
channel
VCO operating frequency
CLKIN duty cycle
Period jitter for CLKIN pin
Duty cycle for DFFIO 1× CLKOUT pin
Period jitter for DIFFIO clock out
Time required for PLL to acquire lock
Multiplication factors for m counter
Multiplication factors for l0, l1, and g0
counter (7),
Minimum pulse width on
signal
CLKIN frequency (1),
Input frequency to PFD
Output frequency for internal global or
regional clock
Output frequency for external clock
driven out on a differential I/O data
channel
VCO operating frequency
CLKIN duty cycle
Period jitter for CLKIN pin
Duty cycle for DFFIO 1× CLKOUT pin
(2)
(8)
Parameter
Tables 4–131
specifications.
(3)
Parameter
(4)
(3)
areset
(3)
through
(6)
(6)
(6)
(6)
4–133
9.375
Min
300
10
10
(5)
40
45
10
10
9.375
1
1
Min
300
10
10
(5)
40
45
describe the Stratix device fast PLL
1,000
±200
Max
717
500
420
100
±200
(5)
60
55
(5)
32
32
Max
640
500
420
700
(5)
60
55
Altera Corporation
January 2006
Integer
Integer
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
μs
ns
%
%
ps
%
%