EP1S30F780I6N Altera, EP1S30F780I6N Datasheet - Page 198

IC STRATIX FPGA 30K LE 780-FBGA

EP1S30F780I6N

Manufacturer Part Number
EP1S30F780I6N
Description
IC STRATIX FPGA 30K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S30F780I6N

Number Of Logic Elements/cells
32470
Number Of Labs/clbs
3247
Total Ram Bits
3317184
Number Of I /o
597
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1S30F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S30F780I6N
Manufacturer:
ALTERA
0
Timing Model
4–28
Stratix Device Handbook, Volume 1
t
t
t
t
t
t
t
EP1S10
EP1S20
EP1S25
EP1S30
SU
H
CO
LUT
CLR
PRE
CLKHL
Table 4–44. LE Internal Timing Microparameters
Table 4–45. IOE Internal TSU Microparameter by Device Density (Part 1 of 2)
Device
Parameter
t
t
t
t
t
t
t
t
SU_R
SU_C
SU_R
SU_C
SU_R
SU_C
SU_R
SU_C
Symbol
1000
Min
100
100
100
10
t
t
t
t
C4
C8
C16
LOCAL
Table 4–43. Routing Delay Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol
-5
76
176
76
76
276
276
76
176
Min
Max
156
366
-5
Delay for a C4 line with average loading; covers a distance of four
LAB rows.
Delay for a C8 line with average loading; covers a distance of eight
LAB rows.
Delay for a C16 line with average loading; covers a distance of 16
LAB rows.
Local interconnect delay, for connections within a LAB, and for the
final routing hop of connections to LABs, DSP blocks, RAM blocks
and I/Os.
Max
1111
Min
100
100
100
10
80
80
80
80
280
280
80
180
-6
Min
Max
176
459
-6
Max
1190
Min
114
114
114
11
80
80
80
80
280
280
80
180
Min
Parameter
-7
-7
Max
202
527
Max
1400
80
80
80
80
280
280
80
180
Min
135
135
135
13
Min
Altera Corporation
-8
-8
Max
Max
238
621
January 2006
ps
ps
ps
ps
ps
ps
ps
ps
Unit
Unit
ps
ps
ps
ps
ps
ps
ps