CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 103

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

13.2
The following registers areassociated with the Comparators in the CY8CTMG20x and CY8CTST200 PSoC devices and are
listed in address order. For a complete table of the comparator registers, refer to the
page
that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow.
Always write reserved bits with a value of ‘0’.
13.2.1
The Comparator Read/Clear Register (CMP_RDC) reads
the state of the comparator data signal and the latched
state of the comparator.
Bit 5: CMP1D. Comparator 1 Data State. This is a read
only bit and returns the dynamically changing state of the
comparator.
Bit 4: CMP0D. Comparator 0 Data State. This bit is a
read-only bit and returns the dynamically changing state
of the comparator.
13.2.2
The Comparator Multiplexer Register (CMP_MUX) con-
tains control bits for input selection of comparators 0 and
1.
Bits 7 and 6: INP1[1:0]. These bits select the positive
input.
Bits 5 and 4: INN1[1:0]. These bits select the negative
input.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
0,78h
LEGEND
#
0,79h
Address
Address
Access is bit specific.
84. Each register description has an associated register table showing the bit structure for that register. Register bits
CMP_MUX
Register Definitions
CMP_RDC
CMP_RDC Register
CMP_MUX Register
Name
Name
Bit 7
Bit 7
INP1[1:0]
Bit 6
Bit 6
CMP1D
Bit 5
Bit 5
INN1[1:0]
CMP0D
Bit 4
Bit 4
Bit 1: CMP1L. Comparator 1 Latched State. This bit is
set and held high whenever the comparator 1 LUT goes
high since the last time this register was read. Refer to the
CRST1 bit in the CMP_CR1 register for information on
how the latch is cleared.
Bit 0: CMP0L. Comparator 0 Latched State. This bit is
set and held high whenever the comparator 0 LUT goes
high since the last time this register was read. Refer to the
CRST0 bit in the CMP_CR1 register for information on
how the latch is cleared.
For additional information, refer to the
on page
Bits 3 and 2: INP0[1:0]. These bits select the positive
input data source for comparator 0.
Bits 1 and 0: INN0[1:0]. These bits select the negative
input data source for comparator 0.
For additional information, refer to the
on page
Bit 3
Bit 3
205.
206.
INP0[1:0]
Bit 2
Bit 2
TrueTouch Register Summary on
CMP1L
Bit 1
Bit 1
INN0[1:0]
CMP0L
CMP_MUX register
CMP_RDC register
Bit 0
Bit 0
Comparators
Access
Access
RW : 00
# : 00
103
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