CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 150

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

Configuration Register
The configuration block contains 1 register. This register must not be changed while the block is enabled. Note that the SPI
Configuration register is located in bank 1 of the PSoC device’s memory map.
18.2.4
The SPI Configuration Register (SPI_CFG) is used to con-
figure the SPI.
Bits 7 to 5: Clock Sel [2:0]. Clock Selection. These bits
determine the operating frequency of the SPI Master.
Bit 4: Bypass. This bit determines whether or not the
inputs are synchronized to SYSCLK.
Bit 3: SS_. Slave Select. This bit determines the logic value
of the SS_ signal when the SS_EN_ signal is asserted
(SS_EN_ = 0).
18.2.4.1
Table 18-5. SPI Configuration Register Descriptions
18.2.5
■
SPI
150
1,29h
Address
Bit #
7:5
IO_CFG1 Register on page 272.
4
3
2
1
0
Clock Sel
Bypass
SS_
SS_EN_
Int Sel
Slave
Name
SPI_CFG
SPI_CFG Register
Related Registers
SPI Configuration Register Definitions
Name
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
Bit 7
Master
Master/Slave
Slave
Slave
Master/Slave
Master/Slave
Mode
Clock Sel[2:0]
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SYSCLK
000b
001b
010b
011b
100b
101b
110b
111b
0 = All pin inputs are doubled, synchronized.
1 = Input synchronization is bypassed.
0 = Slave selected.
1 = Slave selection is determined from external SS_ pin.
0 = Slave selection determined from SS_ bit.
1 = Slave selection determined from external SS_ pin.
0 = Interrupt on TX Reg Empty.
1 = Interrupt on SPI Complete.
0 = Operates as a master.
1 = Operates as a slave.
/ 2
/ 4
/ 8
/ 16
/ 32
/ 64
/ 128
/ 256
Bit 5
Bypass
Bit 4
Bit 2: SS_EN_. Slave Select Enable. This active low bit
determines if the slave select (SS_) signal is driven inter-
nally. If it is driven internally, its logic level is determined by
the SS_ bit. If it is driven externally, its logic level is deter-
mined by the external pin.
Bit 1: Int Sel. Interrupt Select. This bit selects which condi-
tion produces an interrupt.
Bit 0: Slave. This bit determines whether the block func-
tions as a master or slave.
For additional information, refer to the
page
261.
Bit 3
SS_
Description
SS_EN_
Bit 2
Int Sel
Bit 1
SPI_CFG register on
Slave
Bit 0
Access
RW : 00
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