CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 85

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CY8CTST200-24LQXI

Manufacturer Part Number
CY8CTST200-24LQXI
Description
IC MCU 32K FLASH 24UQFN
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet

Specifications of CY8CTST200-24LQXI

Program Memory Type
FLASH (32 kB)
Package / Case
24-WQFN Exposed Pad, 24-HWQFN
Applications
Touchscreen Controller
Core Processor
M8C
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
20
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Mounting Style
SMD/SMT
Program Memory Size
32 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2956

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY8CTST200-24LQXI
Manufacturer:
CY
Quantity:
487
This chapter presents the TrueTouch Module and its associated registers. For a quick reference of all PSoC registers in
address order, refer to the
11.1
11.1.1
A block diagram of the overall capacitive sensing architec-
ture is shown in
capacitors
approaches use different subsets of this hardware.
Figure 11-1. TrueTouch Module Block Diagram
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Vr
11. TrueTouch Module
IMO
Comparator
IDAC
Reference
Buffer
Clock Select
TrueTouch
Architectural Description
Types of TrueTouch Approaches
being
-
+
TrueTouch Counters
Mux
Mux
Figure
CSCLK
measured.
11-1. CS1 through CSN are the
Register Reference chapter on page
Refs
Oscillator (RO)
Relaxation
The
various
C
C
INTERNAL
EXTERNAL
sensing
CS1
CS2
CSN
187.
11.1.1.1
In the positive charge integration method, charge on a
sense capacitor is integrated onto a larger capacitor, starting
from ground. The number of cycles required to reach a tar-
get voltage gives a measurement of the sensed capaci-
tance. The hardware configuration for this approach is
shown in
either pin P0[1] or P0[3] for the external integration capaci-
tor.
Figure 11-2. Positive Charge Integration Block Diagram
Comparator
Vr
Reference
Buffer
IMO
Figure
CSCLK
Positive Charge Integration
TrueTouch Logic
11-2. The hardware supports the use of
Mux
Mux
Clock Select
TrueTouch
16-Bit Counter
CSCLK
Refs
Pin Enables
CSCLK
s
CS1
CS2
CSN
C
P0[1] or
EXTERNAL
P0[3]
[+] Feedback
85

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