CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 213

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

21.3.25 CS_CR2
This register contains additional TrueTouch system control options.
For additional information, refer to the
Bit
7:6
5
4
3
2
1
0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
CS_CR2 : 0,A2h
Access : POR
Bit Name
IRANGE
IDACDIR
IDAC_EN
CIN_EN
PXD_EN
CIP_EN
RO_EN
Name
TrueTouch Control Register 2
7
IRANGE
RW : 0
6
Description
Bits scale the IDAC current output. The IDAC_D register sets the base current in the IDAC.
00b
01b
10b
11b
Bit determines the source/sink state of the IDAC when enabled (IDAC_EN = 1 or PXD_EN = 1 or
CSD_MODE = 1).
0
1
Bit provides manual connection of the IDAC to the analog global bus. The IDAC is automatically con-
nected when RO_EN = 1 or PXD_EN = 1.
0
1
0
1
0
1
0
1
0
1
Register Definitions on page 92
IDAC output scaled to 1X range.
IDAC output scaled to 2X range.
IDAC output scaled to 4X range.
IDAC output scaled to 8X range.
IDAC sources current to analog global bus.
IDAC sinks current from analog global bus.
No manual connection.
IDAC is connected to analog global bus.
Negative charge integration disabled.
Negative charge integration enabled. Selected sense pin(s) alternately connect to the ana-
log global bus and ground. Clock rate is selected by the CLKSEL bits in the CS_CR1 regis-
ter.
No clock to I/O pins.
Enabled pins switch between ground and the analog global bus. Clock rate selected by the
CLKSEL bits in the CS_CR1 register. Selected clock drives TrueTouch timer.
Positive charge integration disabled.
Positive charge integration enabled. Reference buffer and integration capacitor pins alter-
nately connect to analog global bus. Clock rate selected by the CLKSEL bits in the CS_CR1
register.
Relaxation oscillator disabled.
Relaxation oscillator enabled. Charging currents are set by the IRANGE bits and the
IDAC_D register value.
IDACDIR
RW : 0
5
IDAC_EN
RW : 0
4
in the TrueTouch Module chapter .
CIN_EN
RW : 0
3
PXD_EN
RW : 0
2
CIP_EN
RW : 0
1
0,A2h
RO_EN
RW : 0
0,A2h
CS_CR2
0
213
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