CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 279

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

21.4.20 VLT_CR
This register is used to set the trip points for POR and LVD.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 144
Bit
5:4
3
2:0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
VLT_CR: 1,E3h
Access : POR
Bit Name
PORLEV[1:0]
LVDTBEN
VM[2:0]
Name
in the POR chapter.
Voltage Monitor Control Register
7
6
Description
Sets the POR level according to the DC Electrical Specifications in the PSoC device data sheet.
Enables reset of the CPU speed register by LVD comparator output.
Sets the LVD levels per the DC Electrical Specifications in the PSoCdevice data sheet, for those
devices with this feature.
000b
001b
010b
011b
100b
101b
110b
111b
Lowest voltage setting.
Highest voltage setting.
5
PORLEV[1:0]
RW : 0
4
LVDTBEN
RW : 0
3
2
1,E3h
VM[2:0]
RW : 0
Register Definitions on
1
1,E3h
VLT_CR
0
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