CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 299

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
skew
slave device
software
software reset
SRAM
SROM
stack
stack pointer
state machine
sticky
stop bit
switching
switch phasing
synchronous
The difference in arrival time of bits transmitted at the same time, in parallel transmission.
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
A set of computer programs, procedures, and associated documentation concerned with the
operation of a data processing system (for example, compilers, library routines, manuals, and
circuit diagrams). Software is often written first as source code and then converted to a binary
format that is specific to the device on which the code is executed.
A partial reset executed by software to bring part of the system back to a known state. A soft-
ware reset restores the M8C to a known state but not blocks, systems, peripherals, or registers.
For a software reset, the CPU registers (CPU_A, CPU_F, CPU_PC, CPU_SP, and CPU_X) are
set to 0x00. Therefore, code execution begins at Flash address 0x0000.
An acronym for static random access memory. A memory device allowing users to store and
retrieve data at a high rate of speed. The term static is used because, once a value has been
loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is
removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be
accessed in normal user code, operating from Flash.
A stack is a data structure that works on the principle of Last In First Out (LIFO). This means that
the last item put on the stack is the first item that can be taken off.
A stack may be represented in a computer’s inside blocks of memory cells, with the bottom at a
fixed location and a variable stack pointer to the current top cell.
The actual implementation (in hardware or software) of a function that can be considered to con-
sist of a set of states through which it sequences.
A bit in a register that maintains its value past the time of the event that caused its transition has
passed.
A signal following a character or block that prepares the receiving device to receive the next
character or block.
The controlling or routing of signals in circuits to execute logical or arithmetic operations, or to
transmit data between specific points in a network.
The clock that controls a given switch, PHI1 or PHI2, in respect to the switched capacitor (SC)
blocks. The SC blocks have two groups of switches. One group of these switches is normally
closed during PHI1 and open during PHI2. The other group is open during PHI1 and closed dur-
ing PHI2. These switches can be controlled in the normal operation, or in reverse mode if the
PHI1 and PHI2 clocks are reversed.
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock
2. A system whose operation is synchronized by a clock signal.
signal.
Glossary
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