CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 90

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

To start a new count, the EN bit in the CS_CR0 register must
be disabled and enabled again.
Following is a typical capacitance measurement algorithm:
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When the interval ends (for example, with an interrupt), the
counter holds a count related to capacitance.
11.1.2
The internal current DAC provides a bias current for use
with the relaxation oscillator (RO) or for capacitance mea-
surement in successive approximation mode. It can also be
set to supply a sinking or sourcing current to any I/O pin
through the analog global bus connection.
The IDAC current is set by the 8-bit IDAC_D register. In
addition, the two IRANGE bits in the CS_CR2 register pro-
vide additional prescaling range.
11.1.3
The TrueTouch Counter block (see
mized to implement both the charge integration algorithm
and the relaxation oscillator algorithms. The hardware con-
sists of two 8-bit up-counters with capture that can be
optionally chained into a single 16-bit capture counter and
an additional 6-bit counter.
In the charge integration algorithms, a single comparator
channel is an input to the count-enable logic of a 16-bit cap-
ture counter. In this implementation, the counters are
chained to create the higher resolution required. When dis-
abled, the counter is reset; when the enable bit (EN bit in
CS_CR0) is written to a ‘1’, the counter operation starts and
a subsequent comparator trip asserts the capture input. This
algorithm can be operated continuously or in one shot
mode. In one shot mode, the capture event causes the
counters to freeze. The host processor then reads the cur-
TrueTouch Module
90
a. If the START output from the TIMER1 is still ’1’ -
b. If the START is ’0’ (START can become zero before
Select clock prescale (IMO divide by 1, 2, 4, … 256).
Configure the PRS (8 or 12 bits) and let it free-run.
Connect external modulation capacitor (CMOD) to the
analog global bus.
Initialize CMOD with the reference buffer, to VREF.
Enable the sense capacitor, which now switches at the
PRS rate.
Enable the IDAC / Comparator / TrueTouch Counter sys-
tem, set the interval timer's count.
At this point, the analog global bus voltage moves back
and forth around the VREF threshold.
Enable the Interval Timer to start accumulating counts
for the selected interval.
counters start incrementing again.
comparator becomes ’1’ again) - counters stop tog-
gling.
IDAC
TrueTouch Counter
Figure
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
11-13) is opti-
rent count. Select the block interrupt from either the input
capture or the 16-bit overflow.
In the first relaxation algorithm, the 8-bit counters operate
separately. One of the counters is clocked by CSCLK, a
divided version of the internal main oscillator (IMO), and one
is clocked by the relaxation oscillator (RO) formed by the
TrueTouch system. In this configuration, the counters are
enabled simultaneously with a write to the Enable bit. Upon
terminal count of Counter Low, the contents of Counter High
are captured. Use the value of the Counter High capture to
compute the difference between RO and IMO frequency.
Changes in this count then indicate capacitance changes.
In the second relaxation algorithm, a 6-bit counter is clocked
by the relaxation oscillator. A 16-bit chained counter is
formed and clocked by CSCLK, a divided version of the
internal main oscillator (IMO). In this configuration, the
counters are enabled simultaneously with a write to the
Enable bit. Upon terminal count of the 6-bit RO counter, the
contents of the 16-bit counter are captured. Changes in this
count then indicate capacitance changes.
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