CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 104

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

13.2.3
The Comparator Control Register 0 (CMP_CR0) enables
and configures the input range of the comparators.
Bit 4: CMP1EN. This bit enables comparator 1.
13.2.4
The Comparator Control Register 1 (CMP_CR1) config-
ures the comparator output options.
Bit 7: CINT1. This bit connects the comparator 1 output
to the analog output.
Bit 6: CPIN1. This bit selects whether the comparator 1
LUT output or the latched output is routed to a GPIO pin.
Bit 5: CRST1. This bit selects whether the comparator 1
latch is reset upon a register write or by a rising edge from
the comparator 0 LUT output.
Bit 4: CDS1. This bit selects between the comparator 1
LUT and the latched output for the main comparator out-
put that drives to the capacitive sense and interrupt logic.
13.2.5
The Comparator LUT Control Register (CMP_LUT) selects
the logic function.
Bits 7 to 4: LUT1[3:0]. These bits control the selection of
the LUT 1 logic functions that may be selected for the com-
parator channel 1.
Bits 3 to 0: LUT0[3:0]. These bits control the selection of
LUT 0 logic functions that may be selected for the compara-
tor channel 0. The selections are shown in the following
table:
Comparators
104
0,7Ah
0,7Bh
0,7Ch
Address
Address
Address
CMP_CR0
CMP_CR1
CMP_LUT
CMP_CR0 Register
CMP_CR1 Register
CMP_LUT Register
Name
Name
Name
CINT1
Bit 7
Bit 7
Bit 7
CPIN1
Bit 6
Bit 6
Bit 6
LUT1[3:0]
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
CRST1
Bit 5
Bit 5
Bit 5
CMP1EN
CDS1
Bit 4
Bit 4
Bit 4
Bit 0: CMP0EN. This bit enables comparator 0.
For additional information, refer to the
page
Bit 3: CINT0. This bit connects the comparator 0 output
to the analog output.
Bit 2: CPIN0. This bit selects whether the comparator 0
LUT output or the latched output is routed to a GPIO pin.
Bit 1: CRST0. This bit selects whether the comparator 0
latch is reset upon a register write or by a rising edge from
the comparator 1 LUT output.
Bit 0: CDS0. This bit selects between the comparator 0
LUT and the latched output for the main comparator out-
put that drives to the capacitive sense and interrupt logic.
For additional information, refer to the
page
For additional information, refer to the
page
LUTx[3:0]
207.
208.
210.
CINT0
Bit 3
Bit 3
Bit 3
0h: 0000: FALSE
1h: 0001: A .AND. B
2h: 0010: A .AND. B
3h: 0011: A
4h: 0100: A .AND. B
5h: 0101: B
6h: 0110: A .XOR. B
7h: 0111: A .OR. B
8h: 1000: A .NOR. B
9h: 1001: A .XNOR. B
Ah: 1010: B
Bh: 1011: A .OR. B
Ch: 1100: A
Dh: 1101: A .OR. B
Eh: 1110: A. NAND. B
Fh: 1111: TRUE
CPIN0
Bit 2
Bit 2
Bit 2
LUT0[3:0]
CRST0
Bit 1
Bit 1
Bit 1
CMP_CR0 register on
CMP_CR1 register on
CMP_LUT register on
CMP0EN
CDS0
Bit 0
Bit 0
Bit 0
Access
RW : 00
RW : 00
RW : 00
Access
Access
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