CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 151

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

18.3
18.3.1
Figure 18-3
as 0, 1, 2, or 3. These mode numbers are an encoding of
two control bits: Clock Phase and Clock Polarity.
Clock Phase indicates the relationship of the clock to the
data. When the clock phase is '0', it means that the data is
registered as an input on the leading edge of the clock and
the next data is output on the trailing edge of the clock.
When the clock phase is '1', it means that the next data is
output on the leading edge of the clock and that data is reg-
istered as an input on the trailing edge of the clock.
Clock Polarity controls clock inversion. When clock polarity
is set to '1’, the clock idle state is high.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Timing Diagrams
shows the SPI modes that are typically defined
SCLK, Polarity=0 (Mode 0)
SCLK, Polarity=1 (Mode 1)
SCLK, Polarity=0 (Mode 2)
SCLK, Polarity=1 (Mode 3)
SPI Mode Timing
MISO
MISO
MOSI
MOSI
SS_
SS_
MODE 0, 1 (Phase=0) Input on leading edge. Output on trailing edge.
MODE 2, 3 (Phase=1) Output on leading edge. Input on trailing edge.
Figure 18-3. SPI Mode Timing
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
151
SPI
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