CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 205

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

21.3.18 CMP_RDC
This register is used to read the state of the comparator data signal and the latched state of the comparator.
In the table above, reserved bits are grayed table cells and are not described in the bit description section below. Reserved
bits must always be written with a value of ‘0’. For additional information, refer to the
Comparators chapter.
Bit
5
4
1
0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
CMP_RDC : 0,78h
Access : POR
Bit Name
CMP1D
CMP0D
CMP1L
CMP0L
Name
Comparator Read/Clear Register
7
6
Description
Read only bit that returns the dynamically changing state of comparator 1. This bit reads zero when-
ever the comparator is disabled.
Read only bit that returns the dynamically changing state of comparator 0. This bit reads zero when-
ever the comparator is disabled.
This bit reads the latch output for comparator 1. It is cleared by either a write of ‘0’ to this bit, or by a
rising edge of the comparator 0 LUT, depending on the state of the CRST1 bit in the CMP_CR1 reg-
ister.
This bit reads the latch output for comparator 0. It is cleared by either a write of ‘0’ to this bit, or by a
rising edge of the comparator 1 LUT, depending on the state of the CRST0 bit in the CMP_CR1 reg-
ister.
CMP1D
R : 0
5
CMP0D
R : 0
4
3
Register Definitions on page 103
2
0,78h
CMP1L
RC : 0
1
CMP_RDC
CMP0L
RC : 0
0,78h
0
in the
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