CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 29

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Table 2-2. Instruction Set Summary Sorted Alphabetically by Mnemonic
09
0A
0B
0C
0D
0E
0F 10 3
01
02
03
04
05
06
07
38
21
22
23
24
25
26
27
70
41
42
64
65
66
67
68
69
9x
39
3A
3B
3C
3D
73
78
79
7A
7B
30
74
75
Note 1 Interrupt acknowledge to Interrupt Vector table = 13 cycles.
Note 2 The number of cycles required by an instruction is increased by one for instructions that span
10 3
10 3
10 3
11 2
4 2
6 2
7 2
7 2
8 2
9 3
4 2
6 2
7 2
7 2
8 2
9 3
5 2
4 2
6 2
7 2
7 2
8 2
9 3
4 2
9 3
4 1
7 2
8 2
4 1
7 2
8 2
5 2
7 2
8 2
8 3
9 3
4 1
4 1
4 1
7 2
8 2
9 1
4 1
4 1
128 byte page boundaries in the Flash memory space.
ADC A, expr
ADC A, [expr]
ADC A, [X+expr]
ADC [expr], A
ADC [X+expr], A
ADC [expr], expr
ADC [X+expr], expr
ADD A, expr
ADD A, [expr]
ADD A, [X+expr]
ADD [expr], A
ADD [X+expr], A
ADD [expr], expr
ADD [X+expr], expr
ADD SP, expr
AND A, expr
AND A, [expr]
AND A, [X+expr]
AND [expr], A
AND [X+expr], A
AND [expr], expr
AND [X+expr], expr
AND F, expr
AND reg[expr], expr
AND reg[X+expr], expr
ASL A
ASL [expr]
ASL [X+expr]
ASR A
ASR [expr]
ASR [X+expr]
CALL
CMP A, expr
CMP A, [expr]
CMP A, [X+expr]
CMP [expr], expr
CMP [X+expr], expr
CPL A
DEC A
DEC X
DEC [expr]
DEC [X+expr]
HALT
INC A
INC X
Instruction Format
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C, Z
Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
if (A=B) Z=1
if (A<B) C=1
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Flags
76 7
77
Fx 13 2
Ex 7
Cx 5
8x
Dx 5
Bx 5
Ax 5
7C 13 3
7D 7
4F 4
50 4
51 5
52 6
53 5
54 6
55 8
56 9
57 4
58 6
59 7
5A 5
5B 4
5C 4
5D 6
5E 7
5F 10 3
60 5
61 6
62 8
63 9
3E 10 2
3F 10 2
40 4
29 4
2A 6
2B 7
2C 7
2D 8
2E 9
2F 10 3
43 9
44 10 3
71 4
8
5
2
2
2
2
2
2
2
2
3
1
2
2
2
2
2
3
3
2
2
2
2
1
1
2
2
2
2
3
3
1
2
2
2
2
2
3
3
2
INC [expr]
INC [X+expr]
INDEX
JACC
JC
JMP
JNC
JNZ
JZ
LCALL
LJMP
MOV X, SP
MOV A, expr
MOV A, [expr]
MOV A, [X+expr]
MOV [expr], A
MOV [X+expr], A
MOV [expr], expr
MOV [X+expr], expr
MOV X, expr
MOV X, [expr]
MOV X, [X+expr]
MOV [expr], X
MOV A, X
MOV X, A
MOV A, reg[expr]
MOV A, reg[X+expr]
MOV [expr], [expr]
MOV reg[expr], A
MOV reg[X+expr], A
MOV reg[expr], expr
MOV reg[X+expr], expr
MVI A, [ [expr]++ ]
MVI [ [expr]++ ], A
NOP
OR A, expr
OR A, [expr]
OR A, [X+expr]
OR [expr], A
OR [X+expr], A
OR [expr], expr
OR [X+expr], expr
OR reg[expr], expr
OR reg[X+expr], expr
OR F, expr
Instruction Format
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C, Z
Flags
20
18
10
08
7E 10 1
7F
6A
6B
6C
28 11 1
6D
6E
6F
19
1A
1B
1C
1D
1E
1F 10 3
00 15 1
11
12
13
14
15
16
17 10 3
4B
4C
4D
4E
47
48
49
4A 10 3
72
31 4
32 6
33 7
34 7
35 8
36 9
37 10 3
45
46 10 3
5
5
4
4
8
4
7
8
4
7
8
4
6
7
7
8
9
4
6
7
7
8
9
5
7
7
5
8
9
9
4
9
1
1
1
1
1
1
2
2
1
2
2
2
2
2
2
2
3
2
2
2
2
2
3
1
2
2
1
3
3
3
2
2
2
2
2
2
3
3
POP X
POP A
PUSH X
PUSH A
RETI
RET
RLC A
RLC [expr]
RLC [X+expr]
ROMX
RRC A
RRC [expr]
RRC [X+expr]
SBB A, expr
SBB A, [expr]
SBB A, [X+expr]
SBB [expr], A
SBB [X+expr], A
SBB [expr], expr
SBB [X+expr], expr
SSC
SUB A, expr
SUB A, [expr]
SUB A, [X+expr]
SUB [expr], A
SUB [X+expr], A
SUB [expr], expr
SUB [X+expr], expr
SWAP A, X
SWAP A, [expr]
SWAP X, [expr]
SWAP A, SP
TST [expr], expr
TST [X+expr], expr
TST reg[expr], expr
TST reg[X+expr], expr
XOR F, expr
XOR A, expr
XOR A, [expr]
XOR A, [X+expr]
XOR [expr], A
XOR [X+expr], A
XOR [expr], expr
XOR [X+expr], expr
XOR reg[expr], expr
XOR reg[X+expr], expr
Instruction Format
CPU Core (M8C)
Z
C, Z
C, Z
C, Z
C, Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C, Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Flags
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