CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 259

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

21.4
The following registers are all in bank 1 and are listed in address order. Registers that are in both Bank 0 and Bank 1 are
listed in address order in the section titled
21.4.1
This register is one of two registers where the combined value determines the unique drive mode of each bit in a GPIO port.
In register PRTxDM0 there are four possible drive modes for each port pin. Two mode bits are required to select one of these
modes, and these two bits are spread into two different registers (PRTxDM0 and
the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the two Drive Mode register bits
that control the drive mode for that pin (for example, bit[2] in PRT0DM0 and bit[2] in PRT0DM1). The two bits from the two
registers are treated as a group. These are referred to as DM1 and DM0, or together as DM[1:0].
All drive mode bits are shown in the sub-table below ([1 0 ] refers to the combination (in order) of bits in a given bit position);
however, this register only controls the least significant bit (LSb) of the drive mode.
The upper nibble of the PRT4DM0 register returns the last data bus value when read. You need to mask it off prior to using
this information. For additional information, refer to the
Bit
7:0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
PRT0DM0 : 1,00h
PRT4DM0 : 1,10h
Access : POR
Bit Name
Drive Mode 0[7:0]
Name
Bank 1 Registers
PRTxDM0
Port Drive Mode Bit Registers 0
7
PRT1DM0 : 1,04h
6
Description
Bit 0 of the drive mode, for each of 8-port pins, for a GPIO port.
[ 1 0]
0 0 b
0 1 b
1 0 b
1 1 b
Note A bold digit in the table above signifies that the digit is used in this register.
Bank 0 Registers on page
Pin Output High
Resistive
Strong
High Z
High Z
5
Register Definitions on page 59
PRT2DM0 : 1,08h
Pin Output Low
Strong
Strong
High Z
Strong
4
Drive Mode 0[7:0]
RW : 00
188.
3
Reset state. Digital input disabled for zero power.
mode with data bit (PRTxDR register) set high.
Notes
I2C compatible mode. For digital inputs, use this
PRTxDM1 on page
in the GPIO chapter.
PRT3DM0 : 1,0Ch
2
1,00h
260). The bit position of
1
PRTxDM0
1,00h
0
259
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