CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 176

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

20.3.9
The Endpoint Count Register 0 (EPx_CNT0) is used for con-
figuring endpoints 1 through 8.
Bit 7: Data Toggle. This bit selects the data packet's toggle
state. For IN transactions, firmware must set this bit to the
expected state. For OUT transactions, the hardware sets
this bit to the state of the received Data Toggle bit. ‘0‘ is
DATA0. ‘1‘ is DATA1.
Full-Speed USB
176
0,40h
0,42h
0,44h
0,46h
0,48h
0,4Ah
0,4Ch
0,4Eh
Address
EP1_CNT0
EP2_CNT0
EP3_CNT0
EP4_CNT0
EP5_CNT0
EP6_CNT0
EP7_CNT0
EP8_CNT0
Name
EPx_CNT0 Register
Data Toggle
Data Toggle
Data Toggle
Data Toggle
Data Toggle
Data Toggle
Data Toggle
Data Toggle
Bit 7
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Data Valid
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
Bit 4
Bit 6: Data Valid. This bit is used for OUT transactions only
and is read only. It is cleared to '0' if CRC, bit stuffing errors,
or PID errors occur. This bit does not update for some end-
point mode settings. ‘0‘ is error in data received. ‘1‘ is no
error.
Bit 0: Count MSB. This bit is the one MSb of a 9-bit
counter. The LSb are the Data Count[7:0] bits of the
EPx_CNT1 register. Refer to the
more information.
For additional information, refer to the
on page
Bit 3
201.
Bit 2
Bit 1
EPx_CNT1 Register
Count MSB
Count MSB
Count MSB
Count MSB
Count MSB
Count MSB
Count MSB
Count MSB
EPx_CNT0 register
Bit 0
Access
# : 0
# : 0
# : 0
# : 0
# : 0
# : 0
# : 0
# : 0
for
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