CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 135

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

This chapter discusses the System Resets and their associated registers. PSoC devices support several types of resets. The
various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow for user
supplied external reset, and to provide recovery from errant code operation. For a complete table of the System Reset regis-
ters, refer to the
in address order, refer to the
16.1
When reset is initiated, all registers are restored to their
default states. In the
page
tables and elsewhere it is indicated in the Access column
values on the right side of the colon, in the register tables.
Minor exceptions are explained ahead.
The following types of resets occur in the PSoC device:
■
■
■
■
The occurrence of a reset is recorded in the Status and
Control registers (CPU_SCR0 for POR, XRES, and WDR)
or in the System Status and Control Register 1 (CPU_SCR1
for IRESS). Firmware can interrogate these registers to
determine the cause of a reset.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
16. System Resets
Power on Reset (POR). This occurs at low supply volt-
age and is comprised of multiple sources.
External Reset (XRES). This active high reset is driven
into the PSoC device on parts that contain an XRES pin.
Watchdog Reset (WDR). This optional reset occurs
when the watchdog timer expires before being cleared
by user firmware. Watchdog resets default to off.
Internal Reset (IRES). This occurs during the boot
sequence if the SROM code determines that Flash
reads are invalid.
187, this is indicated by the POR row in the register
Architectural Description
Summary Table of the System Resource Registers on page
Register Reference chapter on
Register Reference chapter on page
16.2
Power on Reset and External Reset cause toggling on two
GPIO pins, P1[0] and P1[1], as described ahead and illus-
trated in
mers to synchronize with the PSoC device. All other GPIO
pins are placed in a high impedance state during and imme-
diately following reset.
16.2.1
At power up, the internal POR causes P1[0] to initially drive
a strong high (1) while P1[1] drives a resistive low (0). After
256 sleep oscillator cycles (approximately 8 ms), the P1[0]
signal transitions to a resistive low state. After an additional
256 sleep oscillator clocks, both pins transition to a high
impedance state and normal CPU operation begins. This is
illustrated in the following figure.
Figure 16-1. P1[1:0] Behavior on Power Up
Internal
187.
Reset
P1[0]
P1[1]
POR Trip
Vdd
Point
Figure 16-1
Pin Behavior During Reset
106. For a quick reference of all PSoC registers
GPIO Behavior on Power Up
S1
R0
and
T1
Figure
T1 = T2 = 256 Sleep Clock Cycles
(approximately 8 ms)
R0
R0
T2
16-2. This allows program-
HiZ
HiZ
135
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