CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 211

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

21.3.23 CS_CR0
This register controls the operation of the TrueTouch counters.
Do not write bits [7:1] while the block is enabled. For additional information, refer to the
TrueTouch Module chapter .
Bit
7:6
5
4
3
2:1
0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
CS_CR0 : 0,A0h
Access : POR
Bit Name
CSOUT[1:0]
CSD_PRSCLK
CSD_CS_CLK
CSD_MODE
MODE[1:0]
EN
Name
TrueTouch Control Register 0
7
CSOUT[1:0]
RW : 0
6
Description
These bits select between a number of TrueTouch signals that can be driven to an output pin.
00b
This bit selects between IMO-P or the PRS output as a clock source to drive the main capacitor
switch.
0
1
This bit selects between IMO or IMO-P for the TrueTouch counters to work. Depending on this bit
selection either IMO or IMO-P is sent as the source clock to the clock dividers which generate
CS_CLK as shown in
0
1
This bit enables the CSD mode. When this bit is enabled, the TIMER1 block works on IMO-P (pre-
scaled IMO) clock. This is also an enable for TrueTouch counters to toggle.
Note :
0
1
TrueTouch Counter Mode.
00b
01b
10b
11b
0
1
IN.
01bCS_INT.
10bCOL.
11bCOH.
Select IMO-P.
Select PRS Output.
Select IMO.
Select IMO-P.
Once the CSD_MODE bit is enabled, the IMO-P clock is a free running divider clock that
cannot be stopped and re-started. The IMO-P and the CPU clock are both derived from the
IMO clock but the phase relationship between them is nondeterministic.
Disable CSD mode. Programmable Timer1 works on either CPUCLK/CLK32, (depends on
CLKSEL bit selection in PT1_CFG (0, B3h) register).
Enable CSD mode. When this bit is set to 1, Programmable Timer1 works on IMO-P.
Event Mode. Start in enable, stop on interrupt event.
Pulse Width Mode. Start on positive edge of next input. Stop on negative edge of input.
Period Mode. Start on positive edge of input. Stop on next positive edge of input.
Start in enable, continuous operation until disable.
Counting is stopped and all counter values are reset to zero.
Counters are enabled for counting.
PRSCLK
RW : 0
CSD_
5
Figure 11-13 on page
CSD_CS_
RW : 0
CLK
4
RW : 0
MODE
CSD_
91.
3
Register Definitions on page 92
2
MODE[1:0]
RW : 0
1
0,A0h
RW : 0
0,A0h
CS_CR0
EN
0
in the
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