CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 155
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CY8CTST200-24LQXI
Manufacturer Part Number
CY8CTST200-24LQXI
Description
IC MCU 32K FLASH 24UQFN
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-24LQXI
Program Memory Type
FLASH (32 kB)
Package / Case
24-WQFN Exposed Pad, 24-HWQFN
Applications
Touchscreen Controller
Core Processor
M8C
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
20
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
24 MHz
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Mounting Style
SMD/SMT
Program Memory Size
32 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2956
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8CTST200-24LQXI
Manufacturer:
CY
Quantity:
487
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Overrun status is set if RX Reg Full is still asserted from a
previous byte when a new byte is about to be loaded into the
RX Buffer register. Because the RX Buffer register is imple-
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SCLK (Mode 0)
SCLK (Mode 1)
SCLK (Mode 0)
SCLK (Mode 1)
SS Toggled on Each Byte
SCLK (Mode 0)
SCLK (Mode 1)
S
S
S
S
S
S
SS Forced
SS Toggled on a Message
Low
Basis
Transfer in
Transfer in
Progress
Progress
Transfer in
Figure 18-7. SPI Status Timing for Modes 0 and 1
Progress
mented as a latch, Overrun status is set one-half bit clock
before RX Reg Full status.
See
ships.
Figure 18-7
and
Figure 18-8
Transfer in
Transfer in
Progress
Progress
for status timing relation-
155
SPI
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