CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 109

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options
available in the PSoC devices. For detailed information on specific oscillators, see the individual oscillator chapters in the sec-
tion called
Summary on page
on page
14.1
The PSoC M8C core has a large number of clock sources
that increase the flexibility of the PSoC device, as listed in
Table 14-1
Table 14-1. System Clocking Signals and Definitions
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SYSCLK
CPUCLK
CLK32K
CLKIM0
SLEEP
14. Digital Clocks
Signal
187.
PSoC Core on page
and illustrated in
Architectural Description
Either the direct output of the Internal Main Oscillator or the
direct input of the EXTCLK pin while in external clocking
mode.
SYSCLK is divided down to one of eight possible frequencies
to create CPUCLK, which determines the speed of the M8C.
See the
tion of this chapter.
The Internal Low Speed Oscillators output. See the
OSC_CR0 Register
chapter.
The internally generated clock from the IMO. By default, this
clock drives SYSCLK; however, an external clock may be
used by enabling EXTCLK mode. The IMO can be set to var-
ious frequencies; the default is 12 MHz.
One of four sleep intervals may be selected from 1.95 ms to 1
second. See the
tions section of this chapter.
OSC_CR0 Register
106. For a quick reference of all PSoC registers in address order, refer to the
OSC_CR0 Register
in the Register Definitions section of this
Figure
23. For a complete table of the digital clock registers, refer to the
Definition
in the Register Definitions sec-
14-1.
in the Register Defini-
14.1.1
The Internal Main Oscillator (IMO) is the foundation upon
which almost all other clock sources in the PSoC device are
based. The default mode of the IMO creates a 12 MHz refer-
ence clock that is used by many other circuits in the device.
The PSoC device has an option to replace the IMO with an
externally supplied clock that becomes the base for all of the
clocks the IMO normally serves. The internal base clock net
is called SYSCLK and is driven by either the IMO or an
external clock (EXTCLK).
Whether the external clock or the internal main oscillator is
selected, all device functions are clocked from a derivative
of SYSCLK or are resynchronized to SYSCLK. All external
asynchronous signals and the internal low speed oscillator
are resynchronized to SYSCLK for use in the digital blocks.
The IMO frequency can be adjusted to other frequencies
besides 12 MHz. See the
page
information.
The IMO is discussed in detail in the chapter
Oscillator (IMO) on page
63, in the Internal Main Oscillator chapter, for more
Internal Main Oscillator
63.
Architectural Description on
System Resources Register
Register Reference chapter
Internal Main
109
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