CY8CTST200-24LQXI Cypress Semiconductor Corp, CY8CTST200-24LQXI Datasheet - Page 307

• Manufacturer Part Number: CY8CTST200-24LQXI
• Description: IC MCU 32K FLASH 24UQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-24LQXI

• Program Memory Type: FLASH (32 kB)
• Package / Case: 24-WQFN Exposed Pad, 24-HWQFN
• Applications: Touchscreen Controller
• Core Processor: M8C
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 20
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.71 V to 5.5 V
• Mounting Style: SMD/SMT
• Program Memory Size: 32 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2956

Sleep bits 276
sleep timer 76
SLIMO bit 257
SLP_CFG register 77, 283, 284, 285
SPI 145
SPI bit
SPI Complete bit 192
SPI timing diagrams
SPI_CFG register 150, 261
SPI_CR register 149, 192
SPI_RXR register 148, 191
SPI_TXR register 147, 190
SRAM with USB 166
SROM, See supervisory ROM
SS_ bit 261
SS_EN_ bit 261
stack operations in RAM paging 40
START bit 221, 224, 225
start, how to 16
STK_PP register 43, 235
STOP bit 258
Stop IE bit 239
Stop Status bit 240
summary of registers
supervisory ROM
SWBootReset function in SROM 34
switch operation in digital clocks 110
system resets 135
architecture 145
configuration register 150
control register 149
data registers 147
master data register definitions 148
master function 146
protocol function 145
register definitions 147
slave data register definitions 148
slave function 146
timing diagrams 151
in INT_CLR0 register 242
in INT_MSK0 register 250
SPI mode timing 151
SPIM timing 152
SPIS timing 157
mapping tables 183
PSoC core 24
system resources 106
TrueTouch system 84
architecture 33
Calibrate0 function 37
Calibrate1 function 37
EraseAll function 36
EraseBlock function 36
function descriptions 34
ProtectBlock function 36
ReadBlock function 35
SWBootReset function 34
TableRead function 36
WriteBlock function 35
architecture 135
external reset 139
system resources
T
TableRead function in SROM 36
technical support 16
Timer1/0 bits
timing diagrams
TMP_DRx register 42, 205
Transmit bit 240
Trim bits in IMO_TR register 281, 286
TrueTouch counter 90
TrueTouch module 85
TrueTouch system
TX Reg Empty bit 192
U
units of measure 17
upgrades 16
USB 195
USB, See full-speed USB
USB_CR0 register 171, 195
USB_CR1 register 180, 262
USB_SOFx register 171, 193
USBIO_CR0 register 172, 196
USBIO_CR1 register 172, 197
V
V Monitor bit
VLT_CMP register 144, 280
VLT_CR register 144, 279
functional details 141
pin behavior 135
power modes 141
power on reset 139
register definitions 137
timing diagrams 139
watchdog timer reset 139
architecture 105
overview 14, 105
register summary 106
in INT_CLR0 register 243
in INT_MSK0 register 250
I2C slave 130
sleep and watchdog 79
SPI 151
system resets 139
TrueTouch module 97
architecture 85
register definitions 92
timing diagram 97
types of approaches 85
architecture 83
overview 14, 83
register summary 84
in INT_CLR0 register 243, 245
in INT_MSK0 register 250
Index
307
[+] Feedback