MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 129

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

FCM3–FCM0—Function Code Mask Bits 3–0
DD1, DD0—DSACK Delay Bits 1 and 0
PS1, PS0—Port Size Bits 1 and 0
4-32
This field can be used to mask certain function code bits, allowing more than one
address space type to be assigned to a chip select. Any set bit masks the
corresponding function code bit.
This field determines the number of wait states added before an internal DSACK is
returned for that entry. Table 4-10 lists the encoding for the DD bits.
This field determines whether a given chip select responds with DSACK and, if so,
what port size is returned. Table 4-11 lists the encoding for the PSx bits.
To use the external DSACK response, PS1–PS0 = 11 should be selected to suppress
internal DSACK generation . The DDx bits then have no significance.
The port size field must be programmed for an internal
DSACK
register must be cleared for the DDx bits to have significance.
If external DSACK signals are returned earlier than indicated
by the DDx bits, the cycle will terminate sooner than
programmed. See 4.2.5.2 PORT B for a discussion on using
the internal DSACK generation without using the CS signal.
Freescale Semiconductor, Inc.
response and the FTE bit in the base address
*Use only for 32-bit DMA transfers.
For More Information On This Product,
PS1
0
0
1
1
DD1
0
0
1
1
Table 4-10. DDx Encoding
Table 4-11. PSx Encoding
MC68340 USER’S MANUAL
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PS0
0
1
0
1
DD0
0
1
0
1
External DSACK Response
NOTE:
Three Wait States
Two Wait States
Zero Wait State
One Wait State
Response
16-Bit Port
Reserved*
8-Bit Port
Mode
MOTOROLA