MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 252

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor, Inc.
6.1 DMA MODULE OVERVIEW
The main purpose of the DMA controller module is to transfer data at very high rates,
usually much faster than the CPU32 under software control can handle. The term DMA is
used to refer to the ability of a peripheral device to access memory in a system in the
same manner as a microprocessor does. DMA operations can greatly increase overall
system performance.
The MC68340 DMA module consists of two, independent, programmable channels. The
term DMA is used throughout this section to reference either channel 1 or channel 2 since
the two are functionally equivalent. Each channel has independent request, acknowledge,
and done signals. However, both channels cannot own the bus at the same time.
Therefore, it is impossible to implicitly address both DMA channels at the same time. The
MC68340 on-chip peripherals do not support the single-address transfer mode.
DMA requests may be internally generated by the channel or externally generated by a
device. For an internal request, the amount of bus bandwidth allocated for the DMA can
be programmed. The DMA channels support two external request modes: burst mode and
cycle steal mode.
The DMA controller supports single- and dual-address transfers. In single-address mode,
a channel supports 32 bits of address and 32 bits of data. Only an external request can be
used to start a transfer in the single-address mode. The DMA provides address and
control signals during a single-address transfer. The requesting device either sends or
receives data to or from the specified address (see Figure 6-2). In dual-address mode, a
channel supports 32 bits of address and 16 bits of data. The dual-address transfers can
be started by either the internal request mode or by an external device using the request
signal. In this mode, two bus transfers occur, one from a source device and the other to a
destination device (see Figure 6-3). In dual-address mode, operands are packed or
unpacked according to port sizes and addresses.
Any operation involving the DMA will follow the same basic steps: channel initialization,
data transfer, and channel termination. In the channel initialization step, the DMA channel
registers are loaded with control information, address pointers, and a byte transfer count.
The channel is then started. During the data transfer step, the DMA accepts requests for
operand transfers and provides addressing and bus control for the transfers. The channel
termination step occurs after operation is complete. The channel indicates the status of
the operation in the channel status register.
6-2
MC68340 USER’S MANUAL
MOTOROLA
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