MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 213

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

5.6.2.8.4 Read A/D Register (RAREG/RDREG). Read the selected address or data
register and return the results via the serial interface.
Command Format:
Command Sequence:
Operand Data:
5-76
15
0
Read A/D Register
Write A/D Register
Read System Register
Write System Register
Read Memory Location
Write Memory Location
Dump Memory Block
Fill Memory Block
Resume Execution
Call User Code
Reset Peripherals
No Operation
None
14
0
Command
13
1
12
0
WAREG/WDREG The data operand is written to the specified address or data
RAREG/RDREG
11
0
Freescale Semiconductor, Inc.
Table 5-23. BDM Command Summary
Mnemonic
RDREG/RAREG
For More Information On This Product,
WSREG
RSREG
WRITE
READ
DUMP
CALL
NOP
FILL
RST
GO
10
???
0
MC68340 USER’S MANUAL
Go to: www.freescale.com
9
0
Read the selected address or data register and return the results
via the serial interface.
register.
The specified system control register is read. All registers that can
be read in supervisor mode can be read in BDM.
The operand data is written into the specified system control
register.
Read the sized data at the memory location specified by the long-
word address. The SFC register determines the address space
accessed.
Write the operand data to the memory location specified by the
long-word address. The DFC register determines the address
space accessed.
Used in conjunction with the READ command to dump large blocks
of memory. An initial READ is executed to set up the starting
address of the block and to retrieve the first result. Subsequent
operands are retrieved with the DUMP command.
Used in conjunction with the WRITE command to fill large blocks of
memory. An initial WRITE is executed to set up the starting
address of the block and to supply the first operand. Subsequent
operands are written with the FILL command.
The pipeline is flushed and refilled before resuming instruction
execution at the return PC.
Current PC is stacked at the location of the current SP. Instruction
execution begins at user patch code.
Asserts RESET for 512 clock cycles. The CPU is not reset by this
command. Synonymous with the CPU RESET instruction.
NOP performs no operation and may be used as a null command.
8
1
MS RESULT
"ILLEGAL"
XXX
XXX
7
1
6
0
"NOT READY"
NEXT CMD
LS RESULT
NEXT CMD
5
0
Description
4
0
A/D
3
2
REGISTER
MOTOROLA
1
0