MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 82

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

EXAMPLE B: A system uses error detection and correction on RAM contents. The
designer may:
MOTOROLA
1. Delay DSACK until data is verified and assert BERR and HALT simultaneously to
2. Delay DSACK until data is verified and assert BERR with or without DSACK if
3. Return DSACK prior to data verification; if data is invalid, BERR is asserted on the
4. Return DSACK prior to data verification; if data is invalid, assert BERR and HALT
indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is
valid, assert DSACK (case 1).
data is in error (case 3). This initiates exception processing for software handling of
the condition.
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
on the next clock cycle (case 6). The memory controller can then correct the RAM
prior to or during the automatic retry.
NOTES:
Case
Num
NA — Signal is not asserted in this state
1
2
3
4
5
6
N — Number of the current even bus state (e.g., S2, S4, etc.)
A — Signal is asserted in this bus state
X — Don't care
S — Signal was asserted in previous state and remains asserted in this state
Table 3-4. DSACK , BERR , and HALT Assertion Results
DSACK
DSACK
DSACK
DSACK
DSACK
DSACK
Control
Signal
BERR
HALT
BERR
HALT
BERR
HALT
BERR
HALT
BERR
HALT
BERR
HALT
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Asserted on Rising
NA/A
NA/A
A/S
A/S
NA
NA
NA
NA
NA
NA
NA
NA
N
A
A
A
A
A
A
Edge of State
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N + 2
NA
NA
NA
S
X
S
S
X
S
X
X
A
X
S
S
X
A
A
Normal cycle terminate and continue.
Normal cycle terminate and halt; continue
when HALT negated.
Terminate and take bus error exception,
possibly deferred.
Terminate and take bus error exception,
possibly deferred.
Terminate and retry when HALT negated.
Terminate and retry when HALT negated.
Result
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