MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 235

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

four. If there is no time in the head to perform a prefetch due to a previous trailing write,
then additional time to perform the prefetches must be allotted in the middle of the
instruction or after the tail.
The total number of clocks for bus activity is as follows:
The number of internal clocks (not overlapped by bus activity) is as follows:
Memory read requires two bus cycles at two clocks each. This read time, implied in the tail
figure for the EA, cannot be overlapped with the instruction because the instruction has a
head of zero. An additional two clocks are required for the ADD instruction itself. The total
is 6
appropriate number of clocks to each memory access.
The instruction sequence MOVE.L D0, (A0) followed by LSL.L #7, D2 provides an
example of overlapped execution. The MOVE instruction has a head of zero and a tail of
four because it is a long write. The LSL instruction has a head of four. The trailing write
from the MOVE overlaps the LSL head completely. Thus, the two-instruction sequence
has a head of zero and a tail of zero, and a total execution of 8 rather than 12 clocks.
General observations regarding calculation of execution time are as follows:
5-98
• Any time the number of bus cycles is listed as "X", substitute a value of one for byte
• The time calculated for an instruction on a three-clock (or longer) bus is usually longer
• If the previous instruction has a negative tail, then a prefetch for the current
• Certain instructions requiring an immediate extension word (immediate word EA,
and word cycles and a value of two for long cycles. For long bus cycles, usually add a
value of two to the tail.
than the actual execution time. All times shown are for two-clock bus cycles.
instruction can begin during the execution of that previous instruction.
absolute word EA, address register indirect with displacement EA, conditional
branches with word offsets, bit operations, LPSTOP, TBL, MOVEM, MOVEC,
MOVES, MOVEP, MUL.L, DIV.L, CHK2, CMP2, and DBcc) are not permitted to begin
until the extension word has been in the instruction pipeline for at least one cycle.
This does not apply to long offsets or displacements.
4
(2 Reads
2 = 12 clocks. If bus cycles take more time (i.e., the memory is off-chip), add an
10 Clocks Total
(0 Writes
2 Clocks/Read)
NUMBER OF INSTRUCTION ACCESS CYCLES
Freescale Semiconductor, Inc.
For More Information On This Product,
2 Clocks/Write) = 6 Clocks of Bus Activity
MC68340 USER’S MANUAL
TOTAL NUMBER OF CLOCKS
6 Clocks Bus Activity = 4 Internal Clocks
NUMBER OF WRITE CYCLES
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NUMBER OF READ CYCLES
(1 Instruction Access
8 (2 /1 /0)
2 Clocks/Access)
MOTOROLA