MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 277

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

CCR1, CCR2
U = Unaffected by reset
INTB—Interrupt Breakpoint
INTN—Interrupt Normal
INTE—Interrupt Error
ECO—External Control Option
MOTOROLA
RESET:
INTB
15
U
Setting the interrupt breakpoint bit sets the BRKP bit in the CSR. The logic AND of INTB
and BRKP generates an interrupt request.
If request generation is programmed to be internal (REQ bits = 00), this bit has no
effect.
Single-Address Mode—This bit defines the direction of transfer.
1 = Enables an IRQ when a breakpoint is recognized and the channel is the bus
0 = Does not enable an IRQ when a breakpoint is recognized and the channel is
1 = Enables an IRQ when the channel finishes a transfer without an error condition
0 = Does not enable an IRQ when the channel finishes a transfer without an error
1 = Enables an IRQ when the channel encounters an error on source read (CSR
0 = Does not enable an IRQ when the channel encounters an error on source read,
1 = If request generation is programmed to be external (REQ = 1x), the requesting
0 = If request generation is programmed to be external (REQ = 1x), the requesting
INTN
14
U
master.
the bus master.
(CSR DONE bit is set).
condition.
BES bit is set), destination write (CSR BED bit is set), or configuration for
channel setup (CSR CONF bit is set).
destination write, or configuration for channel setup.
device receives the data (read from memory), and the control signals ( DREQ ,
DACK , and DONE ) are used by the requesting device to write data during the
source (read) portion of the transfer.
device provides the data (write to memory), and the control signals ( DREQ ,
DACK , and DONE ) are used by the requesting device to provide data during
the destination (write) portion of the transfer.
INTE
13
U
ECO
12
U
Freescale Semiconductor, Inc.
SAPI
11
U
For More Information On This Product,
DAPI
10
U
MC68340 USER’S MANUAL
Go to: www.freescale.com
9
U
SSIZE
8
U
7
U
DSIZE
6
U
5
U
REQ
4
U
3
U
BB
Supervisor/User
2
U
$788, $7A8
S/D
1
U
STR
6- 27
0
0