MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 320

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

OE—Overrun Error
TxEMP—Transmitter Empty
TxRDY—Transmitter Ready
FFULL—FIFO Full
RxRDY—Receiver Ready
MOTOROLA
This bit is duplicated in the ISR; bit 0 for channel A and bit 4 for channel B.
1 = One or more characters in the received data stream have been lost. This bit is
0 = No overrun has occurred.
1 = The channel transmitter has underrun (both the transmitter holding register and
0 = The transmitter buffer is not empty. The transmitter holding register is loaded by
1 = The transmitter holding register is empty and ready to be loaded with a character.
0 = The transmitter holding register was loaded by the CPU32, or the transmitter is
1 = A character was transferred from the receiver shift register to the receiver FIFO
0 = The CPU32 has read the receiver buffer and one or more FIFO positions are
1 = A character has been received and is waiting in the FIFO to be read by the
0 = The CPU32 has read the receiver buffer, and no characters remain in the FIFO
set upon receipt of a new character when the FIFO is full and a character is
already in the shift register waiting for an empty FIFO position. When this occurs,
the character in the receiver shift register and its break detect, framing error
status, and parity error, if any, are lost. This bit is cleared by the reset error status
command in the CR.
transmitter shift registers are empty). This bit is set after transmission of the last
stop bit of a character if there are no characters in the transmitter holding register
awaiting transmission.
the CPU32, or the transmitter is disabled. The transmitter is enabled/disabled by
programming the TCx bits in the CR.
This bit is set when the character is transferred to the transmitter shift register.
This bit is also set when the transmitter is first enabled. Characters loaded into
the transmitter holding register while the transmitter is disabled are not
transmitted and are lost.
disabled.
and the transfer caused the FIFO to become full (all three FIFO holding register
positions are occupied).
available. Note that if there is a character in the receiver shift register because
the FIFO is full, this character will be moved into the FIFO when a position is
available, and the FIFO will remain full.
CPU32. This bit is set when a character is transferred from the receiver shift
register to the FIFO.
after this read.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
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