MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 40

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Port B4, B2, B1, AVEC
2.6 INTERRUPT REQUEST LEVEL (IRQ7, IRQ6, IRQ5, IRQ3)
These pins can be programmed to be either prioritized interrupt request lines or port B
parallel I/O.
IRQ7, IRQ6 , IRQ5, IRQ3
Port B7, B6, B5, B3
2.7 BUS CONTROL SIGNALS
These signals control the bus transfer operations of the MC68340. Refer to Section 3
Bus Operation for more information on these signals.
2.7.1 Data and Size Acknowledge ( DSACK1, DSACK0 )
These two active-low input signals allow asynchronous data transfers and dynamic data
bus sizing between the MC68340 and external devices as listed in Table 2-3. During bus
cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol.
During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the
data. During a write cycle, this indicates that the external device has successfully stored
the data and that the cycle may terminate.
2.7.2 Address Strobe ( AS )
AS is an output timing signal that indicates the validity of both an address on the address
bus and many control signals. AS is asserted approximately one-half clock cycle after the
beginning of a bus cycle.
2-6
This signal group functions as three bits of parallel I/O and the autovector input. AVEC
requests an automatic vector during an interrupt acknowledge cycle.
IRQ7 , the highest priority, is nonmaskable. IRQ6–IRQ1 are internally maskable
interrupts. Refer to Section 5 CPU32 for more information on interrupt request lines.
These pins can be used as port B parallel I/O. Refer to Section 4 System Integration
Module for more information on parallel I/O signals.
DSACK
1
1
0
0
1
Freescale Semiconductor, Inc.
For More Information On This Product,
DSACK
Table 2-3. DSACK Encoding
1
0
1
0
0
MC68340 USER’S MANUAL
Go to: www.freescale.com
Insert Wait States in Current Bus Cycle
Complete Cycle—Data Bus Port Size Is 8 Bits
Complete Cycle—Data Bus Port Size Is 16 Bits
Reserved—Defaults to 16-Bit Port Size Can Be
Used for 32-Bit DMA Cycles
Result
MOTOROLA