MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 190

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

MOTOROLA
The TP field defines the class of the faulted bus operation. Two bus error exception
frame types are defined. One is for faults on prefetch and operand accesses, and the
other is for faults during exception frame stacking:
MV is set when the operand transfer portion of the MOVEM instruction is in progress at
the time of a bus fault. If a prefetch bus fault occurs while prefetching the MOVEM
opcode and extension word, both the MV and IN bits will be set.
TR indicates that a trace exception was pending when a bus error exception was
processed. The instruction that generated the trace will not be restarted upon return
from the exception handler. This includes MOVEM and released write bus errors
indicated by the assertion of either MV or RR in the SSW.
B1 indicates that a breakpoint exception was pending on channel 1 (external breakpoint
source) when a bus error exception was processed. Pending breakpoint status is
stacked, regardless of the type of bus error exception.
B0 indicates that a breakpoint exception was pending on channel 0 (internal breakpoint
source) when the bus error exception was processed. Pending breakpoint status is
stacked, regardless of the type of bus error exception.
RR will be set if the faulted bus cycle was a released write. A released write is one that
is overlapped. If the write is completed (rerun) in the exception handler, the RR bit
should be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set
upon return from the exception handler.
Faulted RMW bus cycles set the RM bit. RM is ignored during unstacking.
Instruction prefetch faults are distinguished from operand (both read and write) faults by
the IN bit. If IN is cleared, the error was on an operand cycle; if IN is set, the error was
on an instruction prefetch. IN is ignored during unstacking.
0 = Operand or prefetch bus fault
1 = Exception processing bus fault
0 = MOVEM was not in progress when fault occurred
1 = MOVEM was in progress when fault occurred
0 = Trace not pending
1 = Trace pending
0 = Breakpoint not pending
1 = Breakpoint pending
0 = Breakpoint not pending
1 = Breakpoint pending
0 = Faulted cycle was read, RMW, or unreleased write
1 = Faulted cycle was a released write
0 = Faulted cycle was non-RMW cycle
1 = Faulted cycle was either the read or write of an RMW cycle
0 = Operand
1 = Prefetch
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
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