MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 387

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

The MC68340 includes on-chip circuitry to detect the initial application of power to the
device. Power-on reset (POR), the output of this circuitry, is used to reset both the system
and IEEE 1149.1 logic. The purpose for applying POR to the IEEE 1149.1 circuitry is to
avoid the possibility of bus contention during power-on. The time required to complete
device power-on is power-supply dependent. However, the IEEE 1149.1 TAP controller
remains in the test-logic-reset state while POR is asserted. The TAP controller does not
respond to user commands until POR is negated.
The MC68340 features a low-power stop mode that uses a CPU instruction called
LPSTOP. The interaction of the IEEE 1149.1 interface with LPSTOP mode is as follows:
9.6 NON-IEEE 1149.1 OPERATION
In non-IEEE 1149.1 operation, there are two constraints. First, the TCK input does not
include an internal pullup resistor and should be pulled up externally to preclude mid-level
inputs. The second constraint is to ensure that the IEEE 1149.1 test logic is kept
transparent to the system logic by forcing the TAP controller into the test-logic-reset state,
using either of two methods. During power-on, POR forces the TAP controller into this
state. Alternatively, sampling TMS as a logic one for five consecutive TCK rising edges
also forces the TAP controller into this state. If TMS either remains unconnected or is
connected to V CC , then the TAP controller cannot leave the test-logic-reset state,
regardless of the state of TCK.
9-12
1. Leaving the TAP controller test-logic-reset state negates the ability to achieve
2. The TCK input is not blocked in LPSTOP mode. To consume minimal power, the
3. The TMS and TDI pins include on-chip pullup resistors. In LPSTOP mode, these two
minimal power consumption, but does not otherwise affect device functionality.
TCK input should be externally connected to V
pins should remain either unconnected or connected to V
power consumption.
Freescale Semiconductor, Inc.
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CC
or ground.
CC
to achieve minimal
MOTOROLA