MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 310

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

7.3.4 Multidrop Mode
A channel can be programmed to operate in a wakeup mode for multidrop or
multiprocessor applications. Functional timing information for the multidrop mode is shown
in Figure 7-8. The mode is selected by setting bits 3 and 4 in mode register 1 (MR1). This
mode of operation allows the master station to be connected to several slave stations
(maximum of 256). In this mode, the master transmits an address character followed by a
block of data characters targeted for one of the slave stations. The slave stations have
their channel receivers disabled. However, they continuously monitor the data stream sent
out by the master station. When an address character is sent by the master, the slave
receiver channel notifies its respective CPU by setting the RxRDY bit in the SR and
generating an interrupt (if programmed to do so). Each slave station CPU then compares
the received address to its station address and enables its receiver if it wishes to receive
the subsequent data characters or block of data from the master station. Slave stations
not addressed continue to monitor the data stream for the next address character. Data
fields in the data stream are separated by an address character. After a slave receives a
block of data, the slave station's CPU disables the receiver and initiates the process
again.
MOTOROLA
Figure 7-7. Looping Modes Functional Diagram
CPU
CPU
CPU
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DISABLED
DISABLED
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Rx
Tx
Rx
Rx
Tx
Tx
(c) Remote Loopback
(b) Local Loopback
(a) Automatic Echo
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
RxDx
INPUT
TxDx
OUTPUT
RxDx
INPUT
TxDx
OUTPUT
RxDx
INPUT
TxDx
OUTPUT
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