MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 201

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MC68340AG16E

Manufacturer Part Number
MC68340AG16E
Description
IC MPU 32BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68340AG16E

Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

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5.6.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW. Microprocessor systems
generally provide a debugger, implemented in software, for system analysis at the lowest
level. The BDM on the CPU32 is unique because the debugger is implemented in CPU
microcode.
BDM incorporates a full set of debug options—registers can be viewed and/or altered,
memory can be read or written, and test features can be invoked.
A resident debugger simplifies implementation of an in-circuit emulator. In a common
setup (see Figure 5-18), emulator hardware replaces the target system processor. A
complex, expensive pod-and-cable interface provides a communication path between
target system and emulator.
By contrast, an integrated debugger supports use of a bus state analyzer (BSA) for in-
circuit emulation. The processor remains in the target system (see Figure 5-19), and the
interface is simplified. The BSA monitors target processor operation and the on-chip
debugger controls the operating environment. Emulation is much closer to target
hardware; thus, many interfacing problems (i.e., limitations on high-frequency operation,
AC and DC parametric mismatches, and restrictions on cable length) are minimized.
5.6.1.2 DETERMINISTIC OPCODE TRACKING OVERVIEW. CPU32 function code
outputs are augmented by two supplementary signals that monitor the instruction pipeline.
The IFETCH output signal identifies bus cycles in which data is loaded into the pipeline
and signals pipeline flushes. The IPIPE output signal indicates when each mid-instruction
pipeline advance occurs and when instruction execution begins. These signals allow a
BSA to synchronize with instruction stream activity. Refer to 5.6.3 Deterministic Opcode
Tracking for complete information.
5.6.1.3 ON-CHIP HARDWARE BREAKPOINT OVERVIEW. An external breakpoint input
and an on-chip hardware breakpoint capability permit breakpoint trap on any
5-64
TARGET
SYSTEM
TARGET
MCU
TARGET
SYSTEM
. . .
Figure 5-18. In-Circuit Emulator Configuration
Figure 5-19. Bus State Analyzer Configuration
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
IN-CIRCUIT
EMULATOR
BUS STATE
ANALYZER
.
TARGET
MCU
MOTOROLA

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