MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 302
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MC68340AG16E
Manufacturer Part Number
MC68340AG16E
Description
IC MPU 32BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68340FE25E.pdf
(441 pages)
Specifications of MC68340AG16E
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
16MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
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7.2.9.1 RTSB . When used for this function, this signal can be programmed to be
automatically negated and asserted by either the receiver or transmitter. When connected
to the CTS input of a transmitter, this signal can be used to control serial data flow.
7.2.9.2 OP1. When used for this function, this output is controlled by bit 1 in the OP.
7.2.10 Channel A Clear-To-Send ( CTSA )
This active-low input is the channel A clear-to-send.
7.2.11 Channel B Clear-To-Send ( CTSB )
This active-low input is the channel B clear-to-send.
7.2.12 Channel A Transmitter Ready ( T RDYA )
This active-low output signal is programmable as the channel A transmitter ready or as a
dedicated parallel output, and cannot be masked by the interrupt enable register (IER).
7.2.12.1 T RDYA . When used for this function, this signal reflects the complement of the
status of bit 2 of the channel A status register (SRA). This signal can be used to control
parallel data flow by acting as an interrupt to indicate when the transmitter contains a
character.
7.2.12.2 OP6. When used for this function, this output is controlled by bit 6 in the OP.
7.2.13 Channel A Receiver Ready ( R RDYA )
This active-low output signal is programmable as the channel A receiver ready, channel A
FIFO full indicator, or a dedicated parallel output, and cannot be masked by the IER.
7.2.13.1 R RDYA . When used for this function, this signal reflects the complement of the
status of bit 1 of the ISR. This signal can be used to control parallel data flow by acting as
an interrupt to indicate when the receiver contains a character.
7.2.13.2 FFULLA . When used for this function, this signal reflects the complement of the
status of bit 1 of the ISR. This signal can be used to control parallel data flow by acting as
an interrupt to indicate when the receiver FIFO is full.
7.2.13.3 OP4. When used for this function, this output is controlled by bit 4 in the OP.
MOTOROLA
MC68340 USER’S MANUAL
7- 7
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