MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 287

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

6.9.1.1 DMA CHANNEL OPERATION IN SINGLE-ADDRESS MODE. The following steps
are required to begin a DMA transfer in single-address mode.
Channel Control Register (CCR)
Channel Status Register (CSR)
Function Code Register (FCR)
Address Register (SAR or DAR)
Byte Transfer Counter (BTC)
Channel Control Register (CCR)
6.9.1.2 DMA CHANNEL OPERATION IN DUAL-ADDRESS MODE. The following steps
are required to begin a DMA transfer in dual-address mode.
Channel Control Register (CCR)
MOTOROLA
• Select the direction of transfer if in single-address mode (ECO bit), or select which
• Write a zero to the start bit (STR) to prevent the channel from starting the transfer
• Select the amount by which to increment the source address for a read cycle (SAPI
• Define the transfer size by selecting the source size for a read cycle (SSIZE field) or
• Select external burst request mode or external cycle steal request mode (REQ field).
• Set the S/D bit for signal-address transfer.
• Clear the CSR by writing $7C into it. The DMA cannot be started until the DONE, BES,
• Encode the source function code for a read cycle or the destination function code for a
• Write the source address for a read cycle or the destination address for a write cycle.
• Encode the number of bytes to be transferred.
• Write a one to the start bit (STR) to allow the transfer to begin.
• Write a zero to the start bit (STR) to prevent the channel from starting the transfer
• Select the amount by which to increment the source and destination addresses (SAPI
• Select the source and destination sizes (SSIZE and DSIZE fields).
• Select internal request, external burst request mode, or external cycle steal request
device generates requests if in dual-address mode.
prematurely.
bit) or the destination address for a write cycle (DAPI bit).
by selecting the destination size for a write cycle (DSIZE field).
BED, CONF, and BRKP bits are cleared.
write cycle.
prematurely.
and DAPI bits).
mode (REQ field).
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
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