MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 288

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Channel Status Register (CSR)
Function Code Register (FCR)
Address Registers (SAR and DAR)
Byte Transfer Counter (BTC)
Channel Control Register (CCR)
6.9.2 DMA Channel Example Configuration Code
The following are examples of configuration sequences for a DMA channel in single- and
dual-addressing modes.
***************************************************************************
* MC68340 basic DMA channel register initialization example code.
* This code is used to initialize the 68340's internal DMA channel
* registers, providing basic functions for operation.
* The code sets up channel 1 for external burst request generation,
* single-address mode, long word size transfers.
* Control signals are asserted on the DMA read cycle.
***************************************************************************
Example 1: External Burst Request Generation, Single-Address Transfers.
***************************************************************************
* SIM40 equates
***************************************************************************
MBAR
MODBASE EQU $FFFFF000 SIM40 MBAR address value
***************************************************************************
* DMA Channel 1 equates
DMACH1
DMAMCR1 EQU $0
* Channel 1 register offsets from channel 1 base address
6-38
• If using internal request, select the amount of bus bandwidth to be used by the DMA
• Clear the S/D bit for dual-address transfer.
• Clear the CSR by writing $7C into it. The DMA cannot be started until the DONE,
• Encode the source and destination function codes.
• Write the source and destination addresses.
• Encode the number of bytes to be transferred.
• Write a one to the start bit (STR) to allow the transfer to begin.
(BB field).
BES, BED, CONF, and BRKP bits are cleared.
EQU $780
EQU $0003FF00 Address of SIM40 Module Base Address Reg.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Offset from MBAR for channel 1 regs
MCR for channel 1
Go to: www.freescale.com
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